The present invention relates to a level shift circuit.
In the prior art mixed analog-and-digital LSI, a digital block unit X and an analog block unit Y share a power source 66 as shown in FIG. 4. In general, in such a mixed analog-and-digital LSI, the digital block unit whose voltage can be easily lowered derives power having a lower voltage than in the analog block unit Y so as to reduce power consumption in the digital block unit X, thereby to realize low power consumption.
As shown in FIG. 5, in the mixed analog-and-digital LSI which realizes low power consumption with the above structure generally includes a level shift circuit Z which level-shifts a signal received from the digital block unit (digital circuit) X into a high-voltage signal, and enters the level-shifted signal into the analog block unit (analog circuit) Y which has a different power supply voltage from the digital block unit X.
FIG. 3 is a circuit diagram showing the structure of the prior art level shift circuit Z used in the above-mentioned mixed analog-and-digital LSI.
The structure and behavior of the level shift circuit Z which is composed of CMOS transistors will be described as follows based on FIG. 3. The level shift circuit Z consists of an input unit 41 which operates from a ground potential Vss and a first power source 65, and an output unit 42 which operates from the ground potential Vss and a second power source 66.
The input unit 41 has a first CMOS inverter circuit 45 and a second CMOS inverter circuit 48. The first CMOS inverter circuit 45 has a PMOS transistor 43 and a NMOS transistor 44 arranged in series between the ground potential Vss and the first power source 65, and their gates and drains are connected, respectively. Similarly, the second CMOS inverter circuit 48 has a PMOS transistor 46 and a NMOS transistor 47 arranged in series between the ground potential Vss and the first power source 65, and their gates and drains are connected to each other. The first inverter circuit 45 has an input terminal 49 at which a digital signal is entered from the digital block unit X. The digital signal changes its value between the ground potential Vss and the power supply voltage of the first power source 65. The first inverter circuit 45 has an output terminal 50 connected to the input terminal 51 of the second inverter circuit 48.
The output unit 42 operates from the ground potential Vss and the second power source 66. Between the ground potential Vss and the second power source 66, there are PMOS transistors 53, 54 whose sources are connected to the second power source 66, and NMOS transistors 55, 56 whose sources are connected to the ground potential Vss. A third CMOS inverter circuit 61 is further arranged between the ground potential Vss and the second power source 66. The third CMOS inverter circuit 61 is composed of a PMOS transistor 59 and a NMOS transistor 60 whose respective gates and drains are connected to each other. The PMOS transistor 53 and the NMOS transistor 55 share a drain 57, and the PMOS transistor 54 and the NMOS transistor 56 share a drain 58. The gate of the PMOS transistor 53 is connected to the drain 58 of the PMOS transistor 54 and the NMOS transistor 56, and the gate of the NMOS transistor 55 is connected to the output terminal 52 of the second inverter circuit 48 in the input unit 41. The gate of the PMOS transistor 54 is connected to the drain 57 of the PMOS transistor 53 and the NMOS transistor 55, and the gate of the NMOS transistor 56 is connected to the output terminal 50 of the first inverter circuit 45. The drain 57 of the PMOS transistor 53 and the NMOS transistor 55 is also connected to the input terminal of the third inverter circuit 61. The third inverter circuit 61 has an output terminal 62, which becomes the output of the output unit 42, and further becomes the level-shifted output of the level shift circuit z.
The behavior of the level shift circuit Z shown in FIG. 3 will be described as follows.
When the input unit 41 is supplied with the ground potential Vss and the first power source 65, and the output unit 42 is supplied with the ground potential Vss and the second power source 66, a first input signal, which sets the ground potential Vss low, and the potential of the first power source 65 high, is entered at the input terminal 49 of the first CMOS inverter circuit 45.
First, the case where the first input signal makes a LOW to HIGH transition will be described. The output terminal 50 of the first CMOS inverter circuit 45 changes from a HIGH on the first power source 65 to a LOW on the ground potential. The input terminal 51 of the second CMOS inverter circuit 48 is connected to the output terminal 50 of the first CMOS inverter circuit 45, so the output terminal 52 of the second CMOS inverter circuit 48 changes from a LOW on the ground potential to a HIGH on the first power source 65. As a result, in the output unit 42, the NMOS transistor 56 whose gate is connected to the output terminal 50 of the first CMOS inverter circuit 45 is turned off, and the NMOS transistor 55 whose gate is connected to the output terminal 52 of the second CMOS inverter circuit 48 is turned on.
At this moment, the gate of the PMOS transistor 54 goes low, and the PMOS transistor 54 is turned on because the gate of the PMOS transistor 54 is connected to the drain of the NMOS transistor 55. This makes the drain 58 of the PMOS transistor 54 change to a HIGH on the second power source 66.
The gate of the PMOS transistor 53, which is connected to the drain 58 of the PMOS transistor 54, changes to a HIGH on the second power source 66, and the PMOS transistor 53 is turned off. As a result of thus turning the PMOS transistor 53 off and the NMOS transistor 55 on, the drain 57 shared by these transistors goes low.
The input of the inverter circuit 61 operating from the second power source 66 is connected to the drain 57 shared by the two MOS transistors 53 and 55, so the output terminal 62 changes to a HIGH on the second power source 66.
The following is a description of the case where the first input signal makes a HIGH to LOW transition. The output terminal 50 of the first CMOS inverter circuit 45 changes from a LOW on the first power source 65 to a high, and the output terminal 52 of the second CMOS inverter circuit 48 changes from a HIGH on the first power source 65 to a LOW on the ground potential because the input terminal 51 of the second CMOS inverter circuit 48 is connected to the output terminal 50 of the first CMOS inverter circuit 45. As a result, in the output unit 42, the NMOS transistor 56 whose gate is connected to the output terminal 50 of the first CMOS inverter circuit 45 is turned on, and the NMOS transistor 55 whose gate is connected to the output terminal 52 of the second CMOS inverter circuit 48 is turned off.
At this moment, the gate of the PMOS transistor 54, which is connected to the drain 57 of the NMOS transistor 55, goes high, and the PMOS transistor 54 is turned off. As a result, the drain 58 of the PMOS transistor 54 changes to a LOW on the ground potential.
The gate of the PMOS transistor 53, which is connected to the drain 58 of the PMOS transistor 54, changes its potential to a LOW on the ground potential, and the PMOS transistor 53 is turned on. By thus turning the PMOS transistor 53 on and the NMOS transistor 55 off, the drain 57 shared by these transistors changes to a HIGH on the power supply voltage of the second power source 66. Since the input of the inverter circuit 61 operating from the second power source 66 is connected to the shared drain 57, the potential of the output terminal 62 of the output unit 42 changes to a LOW on the ground potential.
As described hereinbefore, the level shift circuit Z shown in FIG. 3 level-shifts a signal entered at the input terminal 49 from the power supply voltage of the first power source 65 to the power supply voltage of the second power source 66, without changing the polarity of the signal.
The prior art level shift circuit operates normally as described above in the normal operation mode when the first and second power sources 65, 66 are both supplied; however, the circuit has a drawback that the output unit 42 suffers from a through current which flows in the following special mode. This problem will be detailed as follows.
In the mixed analog-and-digital LSI, when the digital block unit X is not employed, it is general to set the power down mode for interrupting the power supply from the first power source 65 to the digital block unit X so as to reduce power consumption in the digital block unit X. The power down mode of the digital block unit X involves a problem, which will be detailed as follows.
When the prior art level shift circuit shown in FIG. 3 is used in a mixed analog-and-digital LSI, the structure is as shown in FIG. 5. To be more specific, the level shift circuit Z and the digital block unit X generally share the first power source 65. In this case, when the first power source 65 is interrupted in the power down mode to reduce power consumption in the digital block unit X, the following problem will occur. In the level shift circuit shown in FIG. 3, when the first power source 65 is shut off from the input unit 41, which shares the first power source 65 with the digital block unit X, the output terminal 50 of the first CMOS inverter circuit 45 and the input and output terminals 51, 52 of the second CMOS inverter circuit 48 which operate from the first power source 65 have indefinite potentials. When the threshold voltage of a PMOS transistor is referred to as Vtp and the threshold voltage of a NMOS transistor is referred to as Trn, if the following conditions hold: the ground voltage Vss+Vtn less than the potential of the output terminal 50, and the ground voltage Vss+Vtn less than the potential of the output terminal 52, then the NMOS transistor 56 whose gate is connected to the output terminal 50 of the first CMOS inverter circuit 45 is turned on, and the NMOS transistor 55 whose gate is connected to the output terminal 52 of the second CMOS inverter circuit 48 is also turned on. At this moment, the gate of the PMOS transistor 54, which is connected to the drain 57 of the NMOS transistor 55, goes low, and the PMOS transistor 54 is turned on. The gate of the PMOS transistor 53, which is connected to the drain 58 of the PMOS transistor 54, changes to a LOW on the ground, and the PMOS transistor 53 is also turned on. As a result of thus turning the PMOS transistors 53, 54 and the NMOS transistors 55, 56 all on, a through current flows from the second power source 66 towards the ground Vss.
Since the potential of the node (shared drain) 57 is determined by the division ratio of the on-resistance between the PMOS transistor 53 and the NMOS transistor 55, when the potential of the node 57 gets close to the switching level of the third inverter circuit 61, the through current also flows in the third inverter circuit 61.
For the above-mentioned reasons, the prior art level shift circuit shown in FIG. 3 has a problem of developing a through current in the power down mode, which leads to an increase in power consumption.
The object of the present invention is to provide a level shift circuit and a mixed analog-and-digital LSI with low power consumption by eliminating the influence of an indefinite node in the level shift circuit which results from a voltage condition of the first power source so as to prevent the development of a through current.
In order to achieve the object, the present invention provides the output unit of the level shift circuit with a unit for cutting off a through current.
TO be more specific, a level shift circuit of the present invention comprises: an input unit which is connected to a first power source and a ground, and receives a signal changing between a ground potential and a power supply potential of the first power source; an output unit which is connected to a second power source and the ground, and receives a signal outputted from said input unit, voltage-shifts the signal into a signal changing between the ground potential and a power supply potential of the second power source and outputs a voltage-shifted signal; cut off means for cutting off a through current path from the second power source to the ground via said output unit; and a potential detection circuit for detecting a time when the first power source is interrupted and generating a control signal for controlling said cut off means.
Another level shift circuit of the present invention comprises: an input unit which is connected to a first power source and a ground, and receives a signal changing between a ground potential and a power supply potential of the first power source; an output unit which is connected to a second power source and the ground, and receives a signal outputted from said input unit, voltage-shifts the signal into a signal changing between the ground potential and a power supply potential of the second power source and outputs a voltage-shifted signal; cut off means for cutting off a through current path from the second power source to the ground via said output unit, said cut off means receiving from outside a signal for cutting off said through current path when the first power source is interrupted.
Furthermore, in each of the level shift circuits of the present invention, said input unit receives said signal changing between said ground potential and said power supply potential of the first power source from a digital circuit, and said output unit outputs said voltage-shifted signal changing between said ground potential and said power supply potential of the second power source to an analog circuit.
As described hereinbefore, according to the present invention, when the first power source to be provided to the input unit of the level shift circuit is interrupted, the output unit is going to have a current path from the second power source to the ground; however, the current path is cut off by the cut off means as a result that the voltage detection circuit detects the interruption of the first power source or that an outside control signal is entered at the output unit. Consequently, the flow of the through current from the second power source towards the ground is prevented securely.